8bit Multiplier Verilog Code Github ~repack~ Access

module mult_8bit_comb ( input [7:0] a, b, output reg [15:0] product ); always @(*) begin product = a * b; // Synthesized into LUTs or DSP slices end endmodule

| Test Case | A | B | Expected Product | Actual Product | Status | |-----------|---|---|------------------|----------------|--------| | 1 | 12 | 34 | 408 | 408 | ✓ PASS | | 2 | 255 | 255 | 65025 | 65025 | ✓ PASS | | 3 | 0 | 128 | 0 | 0 | ✓ PASS | | 4 | 100 | 200 | 20000 | 20000 | ✓ PASS | 8bit multiplier verilog code github

endmodule